It used to be that designing hardware required schematics and designing software required code. Sure, a lot of people could jump back and forth, but it was clearly a different discipline. Today, a lot ...

In FPGA design, where timing is everything, there are tips and tricks to help designers set up clocks, correctly set timing constraints and then tune parameters of the FPGA, write Angela Sutton and ...

Last time, we looked at getting started with the GOWIN tools and a Tang Nano 20K FPGA. The software from GOWIN isn’t bad, but ...

Californian start-up Achronix has revealed details of its 1.5GHz asynchronous FPGA, which includes 10.3Gbit/s serialiser/deserialisers (serdes). “We get our speed from the underlying silicon ...

Flexibility is key to FPGA success, but speed is equally important. Achronix almost triples the throughput of the system by taking clock gating to the extreme. The Achronix Speedster FPGAs use a ...

No discussion on FPGA design is complete without addressing the issues associated with transferring signals that are not synchronized to the clock into clocked logic. While this should be a digital ...

Over a few short years, FPGA technology has advanced significantly. These devices have become extremely complex. FPGA blocks continue to maintain the phase-locked loop (PLL) technology capable of ...

The checkbox is the enemy of a successful ASIC tapeout or FPGA/system release into production. This is counter-intuitive, as the checklist is critical in ensuring that process is followed and that ...

Clock signals in synchronous digital systems (such as those found in telecommunications) define when and how quickly data is moved through that system. A clock distribution network, consisting of ...

Clock domain crossing (CDC) issues cause significant amount of failures in ASIC and FPGA devices. As FPGA complexity and performance grows, the influence of CDC issues on design functionality grows ...